module lpuart_apb_biu(
input             pclk,
input             presetn,
input             psel,
input             penable,
input             pwrite,
input      [7:0]  paddr,
input      [31:0] pwdata,
output reg [31:0] prdata,

// register block interface signals
input      [31:0] iprdata,

output            wr_en,
output            rd_en,
output     [5:0]  reg_addr,
output reg [31:0] ipwdata
);

assign wr_en = psel & penable & pwrite;
assign rd_en = psel & !penable & !pwrite;

assign reg_addr = paddr[7:2];

always@(*)begin
  ipwdata = {32{1'b0}};
  ipwdata = pwdata;
end

always@(posedge pclk, negedge presetn) begin:PRADTA_PROC
  if(!presetn) begin 
    prdata <= {32{1'b0}};
  end else begin
    if(rd_en) begin
      prdata <= iprdata;
    end
  end
end

endmodule
